1. Field of the Invention
The present invention relates to dry etching a material such as polycrystalline silicon and silicides with hydrogen bromide or bromine.
2. Description of the Related Art
As a result of the increased degree of integration and switching speed of integrated circuits IC's, an insulating film such as a gate insulating film must be made thinner, for example, 30 nm to 50 nm, and further, a multilayer technology for electrical conductive materials such as polycrystalline silicon must be utilized. This processing of such a polycrystalline silicon determines rate length, which influences the characteristics of an field effect transistor FET, and thus during etching of the polycrystalline silicon, the width of a pattern must be strictly controlled and a high etching selectivity of the polycrystalline silicon obtained in relation to an underlying gate insulating layer. To accomplish the above, vertical etching methods, such as reactive ion etching, can be used, but if a lower layer, for example, a first polycrystalline silicon layer, is vertically etched, the thickness of an upper layer, for example, a second polycrystalline silicon layer, becomes thicker at a portion of a step of the vertically etched first polycrystalline silicon layer than at the other flat portion. This thicker portion of the second polycrystalline silicon layer remains after the second polycrystalline silicon layer is etched, and leads to a short circuiting of adjacent patterns of the second polycrystalline silicon layer through the remaining portion. If the second polycrystalline silicon layer is over-etched for an extended time, to completely remove the polycrystalline silicon at the step portion, the width of a pattern is narrowed and the underlying insulating layer is excessively etched.
One solution to the above problems is the use of a vertical etching process having a high selectivity, so that an underlying layer is not excessively etched. To obtain this high selectivity, a chlorine-bearing or fluorine-bearing etching gas is widely used, but etching with a chlorine or fluorine-bearing gas tends to cause side-etching, due to the isotropic nature thereof, and it becomes difficult to control the width of a pattern. To protect the side wall of a pattern from such an etching gas, a carbon-bearing gas may be used, but use of a carbon-bearing gas increases the etching rate of an insulating layer, whereby the selectivity of etching of a polycrystalline silicon, etc. in relation to an insulating layer is reduced. Further, a polymer containing carbor is deposited onto a wall of an etching chamber, which causes contamination and a reduction of the product yield.
Another solution is to form a pattern of a first polycrystalline silicon layer having a tapered shape, i.e., a declined, not vertical, side wall, on which a second polycrystalline silicon layer is deposited and then etched.
The known methods of taper etching are as follows:
(1) Phosphorus is diffused and phosphorus ions are then implanted to a first polycrystalline silicon layer, to make the ion implanted surface portion of the layer more receptive to etching. Then isotropic etching is carried out on the polycrystalline silicon layer, and thus the polycrystalline silicon layer is taper etched. [Japanese Unexamined Patent Publication Nos. 58-4932 and 53-73086 and Japanese Examined Patent Publication No. 60-782]. Nevertheless, this process is complicated, since a diffusion of phosphorus and ion implantation is necessary before the etching. Also, it is difficult to control a width of a pattern during isotropic etching.
(2) Etching with an etching gas to which a depositing gas such as C.sub.2 H.sub.6, C.sub.2 H.sub.4, is added to provide a simultaneous etching and deposition to form a tapered pattern. (Japanese Unexamined Patent Publication Nos. 59-103338, 62-30330 and 62-32618]. This method allows a deposition on a wall of an etching chamber, which results in contamination by particles and reduces the product yield.
(3) A resist mask is tapered and etching is effected with a low etching selectivity between polycrystalline silicon and the resist. [Japanese Unexamined Patent Publication (Kokai) No. 61-61424]. In this method, since the thickness of the resist is varied, it is difficult to control the width of a pattern.
(4) Alternate etching and ashing of a resist mask. [Japanese Unexamined Patent Publication (Kokai) No. 56-93319 and 57-59331]. This process is complicated and control of the width of a pattern is difficult, since the thickness of the resist mask is reduced.
(5) Isotropic etching followed by anisotropic etching. The isotropic etching is stopped when only an upper part of a polycrystalline silicon layer is etched, and then the anisotropic etching is carried out. [Japanese Unexamined Patent Publication No. 57-7936 and 56-90525]. This process also is complicated, and the control of the width of a pattern is difficult.
(6) A mask having an overhanging portion having a lower surface facing upward is used, so that the flow of ions is disturbed and thus a tapered pattern is formed. [Japanese Examined Patent Publication No. 57-42154]. It is not easy, however, to form a resist mask having an overhanging portion as above, and it is difficult to control the width of an etched pattern.
Therefore, the main object of the present invention is to provide a process for anisotropically etching a material such as polycrystalline silicon and silicides, which process is simple and easily controlled. Another object of the present invention is to provide a process for taper etching such a material, which process is simple and able to control the taper angle of an etched pattern. A further object of the present invention is to provide a process for vertically etching such a material with a high etching selectivity, without side-etching.